This invention relates generally to metal compound chemically anchored colloidal particles, the methods of production and use thereof.
The metal compound chemically anchored colloidal particles, more specifically, are colloidal particles having metal compounds uniformly anchored to the surfaces via chemical bonding. The metal compounds are in molecular form. The metal compound chemically anchored colloidal particles can be widely used in the industry, for example, to act as catalyst to increase the reaction rates for a range of different processes. For example, they can be used as a solid catalyst in chemical-mechanical planarization (CMP) of semiconductor wafers.
There are a large number of materials used in the manufacture of integrated circuits such as a semiconductor wafer. The materials generally fall into three categories—dielectric material, adhesion and/or barrier layers, and conductive layers. The use of the various substrates, e.g., dielectric material such as TEOS, plasma-enhanced TEOS (PETEOS), and low-k dielectric materials; barrier/adhesion layers such as tan copper, tantalum, titanium, tantalum nitride, and titanium nitride; and conductive layers such as aluminum, tungsten, and noble metals are known in the industry.
Integrated circuits are interconnected through the use of well-known multilevel interconnections. Interconnection structures normally have a first layer of metallization, an interconnection layer, a second level of metallization, and typically third and subsequent levels of metallization. Interlevel dielectric materials such as silicon dioxide and sometimes low-k materials are used to electrically isolate the different levels of metallization in a silicon substrate or well. The electrical connections between different interconnection levels are made through the use of metallized vias and in particular tungsten vias. U.S. Pat. No. 4,789,648 describes a method for preparing multiple metallized layers and metallized vias in insulator films. In a similar manner, metal contacts are used to form electrical connections between interconnection levels and devices formed in a well. The metal vias and contacts are generally filled with tungsten and generally employ an adhesion layer such as titanium nitride (TiN) and/or titanium to adhere a metal layer such as a tungsten metal layer to the dielectric material.
W (tungsten) has been a widely used material for the formation of contact, via and hole for connecting the inter-layer metal lines in IC fabrication due to its excellence in filling vias by Chemical Vapor Deposition (CVD).
In a typical process, via holes are etched through the interlevel dielectric (ILD) to interconnection lines or to a semiconductor substrate. Next, a thin adhesion layer such as titanium nitride and/or titanium is generally formed over the ILD and is directed into the etched via hole. Then, a tungsten film is blanket deposited over the adhesion layer and into the via. The deposition is continued until the via hole is filled with tungsten. Finally, the excess tungsten is removed by chemical mechanical polishing (CMP) to form contacts and vias.
In a typical CMP process, a substrate (e.g., a wafer) is placed in contact with a rotating polishing pad attached to a platen. A CMP slurry, typically an abrasive and chemically reactive mixture, is supplied to the pad during CMP processing of the substrate. During the CMP process, the pad (fixed to the platen) and substrate are rotated while a wafer carrier system or polishing head applies pressure (downward force) against the substrate. The slurry accomplishes the planarization (polishing) process by chemically and mechanically interacting with the substrate film being planarized due to the effect of the rotational movement of the pad parallel to the substrate. Polishing is continued in this manner until the desired film on the substrate is removed with the usual objective being to effectively planarize the substrate. Typically metal CMP slurries contain an abrasive material, such as silica or alumina, suspended in an oxidizing, aqueous medium.
The ratio of the removal rate of a metal (e.g., tungsten) to the removal rate of a dielectric base is called the “selectivity” for removal of the metal in relation to removal of the dielectric during CMP processing of substrates comprised of metal and dielectric material.
When CMP slurries with high selectivity for removal of metal in relation to dielectric are used, the metal layers are easily over-polished creating a depression or “dishing” effect in the metalized areas. This feature distortion is unacceptable due to lithographic and other constraints in semiconductor manufacturing.
Another feature distortion that is unsuitable for semiconductor manufacturing is called “erosion.” Erosion is the topography difference between a field of dielectric and a dense array of metal vias or trenches. In CMP, the materials in the dense array may be removed or eroded at a faster rate than the surrounding field of dielectric. This causes a topography difference between the field of dielectric and the dense metal (e.g., copper or tungsten) array.
As industry standards trend toward smaller device features, there is a continuous developing need for tungsten CMP slurries that deliver superior planarization of the nanostructures of IC chips. Specifically, for 28 nm technology nodes and beyond applications, slurry products must deliver tunable removal rate and tunable selectivity between metal and dielectric, reduce the erosion and dishing while maintaining sufficient removal rate.
The slurry chemistry plays a major role in removing the W material by CMP process. The W slurry should consist of suitable abrasives with appropriate chemicals to meet the requirements. Usually an oxidizer is added to W slurry since it plays a key role in increasing the removal rate by forming the passive tungsten oxide layer, which is softer than W material, onto the surface and this surface is mechanically abraded by abrasive particles.
Colloidal silica plays a key role as a polishing slurry for CMP process. Several attempts have been done in modifying these slurries to make it suitable for the CMP process for different materials and applications.
Recently work has been performed on coating of the catalyst to the abrasive to enhance the chemical reaction between oxidizing agent and the metal to be polished during CMP process.
U.S. Pat. No. 4,478,742 discloses a method of producing iron acetate coated silica sol comprising the steps of passing a mixture of ion free colloidal silica and an inorganic iron salt in contact with a strong base anion exchange resin in the acetic acid salt form under conditions whereby the iron salt is converted to the iron acetate and is coated on the silica sol, thereby producing an iron acetate coated silica sol.
U.S. Pat. Nos. 7,014,669, 7,029,508 and 7,427,305 teach a composition for chemical mechanical polishing which comprises at least one abrasive particle having a surface at least partially coated by a catalyst. The catalyst comprises a metal other than a metal of Group 4(b), Group 5(b) or Group 6(b). The composition further comprises at least one oxidizing agent. The composition is believed to be effective by virtue of the interaction between the catalyst coated on the surface of the abrasive particles and the oxidizing agent, at the catalyst surface. The invention further provides a method that employs the composition in the polishing of a feature or layer, such as a metal film, on a substrate surface. The invention additionally provides a substrate produced this method.
Young-Jae Kang et al (J. Colloid & Inter. Sci. 2010, 349, 402-407) disclose a new method of Fe (metal) precipitation on colloidal silica to overcome the stability problem, which would be responsible in producing defects, with commercially available fumed silica slurry containing Fe ions. More specifically, Young-Jae Kang et al have synthesized colloidal silica particles using sodium silicate (Na2SiO3) as raw material with and without Fe precipitation by ion exchange process.
J. Colloid & Inter. Sci. 2005, 282, 11-19, studied the synthesis and characterization of iron oxide-coated silica. A three-level fractional factorial study was used to determine the optimum conditions for producing goethite-coated silica. The amount of coating achieved was between 0.59 and 21.36 mg Fe g−1 solid. The most significant factor in coating using either adsorption or precipitation was the particle size of silica, where Fe increased from an average of 0.85 to 9.6 mg Fe g−1 solid as silica size decreased from 1.5 to 0.2 mm. Other factors investigated, including coating temperature, initial iron concentration, and contact time, were of less importance. The iron oxide coatings were observed to be non-uniform, concentrated in rough concave areas. FTIR revealed a band shift as well as a new band indicating changes in the chemical environment of Fe—O and Si—O bonds; these results along with abrasion studies suggest that the interaction between the oxide coating and silica surface potentially involves chemical forces. Because the nano-sized iron oxide coatings increased surface area, introduced small pores, and changed the surface charge distribution of silica, the coated system demonstrates a greater affinity for Ni compared to that of uncoated silica.
US2013/0068995 discloses a silica having metal ions absorbed thereon and a fabricating method thereof are provided. The silica having metal ions absorbed thereon is a silica having metal ions absorbed thereon and being modified with persulfate salt. The method includes following steps. A solution is provided, and the solution includes silica and persulfate salt therein. The solution is heated to react the silica with the persulfate salt, so as to obtain silica modified with persulfate salt. Metal ion source is added in the solution, the metal ion source dissociates metal ions, and the silica modified with persulfate salt absorbs the metal ions to obtain the silica having metal ions absorbed thereon.
There is a significant need for tungsten CMP process(es) and slurry(s) that afford low dishing and plug recess effects especially in view of the fact that the semiconductor industry continues to move towards smaller and smaller feature sizes.